1. Field of the Invention
The present invention relates in general to restore circuits for semiconductor memory devices for supplying a restore voltage to a sense amplifier using an internal supply voltage and an external supply voltage, and more particularly to a restore circuit for a semiconductor memory device which is capable of generating a restore voltage which is stable with respect to a variation in the external supply voltage, with no increase in the number of manufacturing processes and no degradation in the drive capability.
2. Description of the Prior Art
Generally, a semiconductor memory device such as a dynamic random access memory comprises a restore circuit for generating a high restore voltage in response to an external supply voltage Vext from an external power supply circuit and an internal supply voltage Vint from an internal voltage down converter. The restore circuit supplies the generated restore voltage to a sense amplifier, thereby allowing the sense amplifier to sense and amplify a data signal transferred thereto through a bit line. To this end, such a conventional restore circuit may comprise two PMOS transistors having their bias electrodes connected in common to an external supply voltage source. Alternatively, another conventional restore circuit may comprise two PMOS transistors having their bias electrodes connected respectively to an internal supply voltage sourced and the external supply voltage source.
However, the above-mentioned first conventional restore circuit has a disadvantage in that the drive capability is degraded due to an overshoot of the external supply voltage Vext and the above-mentioned second conventional restore circuit has a disadvantage in that additional manufacturing processes are required to prevent a latch-up phenomenon. The above problems with the conventional restore circuits will hereinafter be described in detail with reference to FIGS. 1 to 4.
Referring to FIG. 1, there is shown a circuit diagram of an example of a conventional restore circuit for a semiconductor memory device. As shown in this drawing, the conventional restore circuit comprises a first PMOS transistor Q1 having its gate for inputting a first control signal from a first input line 11, and a second PMOS transistor Q2 having its gate for inputting a second control signal from a second input line 12. The first PMOS transistor Q1 has its source and bias electrode connected in common to an external supply voltage source and its drain connected to an output line 13, which is connected to a sense amplifier (not shown). When the first control signal from the first input line 11 is low in logic, the first PMOS transistor Q1 is turned on and then remains at its ON state until a restore voltage of a precharge level Vint/2 on the output line 13 is boosted to an internal supply voltage Vint from an internal supply voltage source. As a result, the first PMOS transistor Q1 acts to prevent the restore voltage on the output line 13 from being varied above the internal supply voltage Vint from the internal supply voltage source.
The second PMOS transistor Q2 has its source connected to the internal supply voltage source, its bias electrode connected to the external supply voltage source and its drain connected to the output line 13. When the second control signal from the second input line 12 is low in logic, the second PMOS transistor Q2 is turned on to transfer the internal supply voltage Vint from the internal supply voltage source to the output line 13. As a result, the second PMOS transistor Q2 acts to maintain the restore voltage on the output line 13 at the internal supply voltage level Vint. The second PMOS transistor Q2 remains at its ON state for an interval from the turning-on of the first PMOS transistor Q1 to a low to high transition of the second control signal after the turning-off of the first PMOS transistor Q1.
FIG. 2 is a sectional view illustrating a structure of the conventional restore circuit for the semiconductor memory device in FIG. 1. As shown in this drawing, formed over a semiconductor substrate 20 is an N-type well 21 in which first to fourth P.sup.- -type impurity regions 22-25 and an N.sup.+ type impurity region 26 are formed. A first gate electrode 27 is formed over a channel region between the first and second P'-type impurity regions 22 and 23. A second gate electrode 28 is formed over a channel region between the third and fourth P.sup.+ -type impurity regions 24 and 25. The first and second P.sup.+ -type impurity regions 22 and 23 are source and drain regions, respectively, and constitute the first PMOS transistor Q1 together with the first gate electrode 27. The third and fourth P.sup.- -type impurity regions 24 and 25 are drain and source regions, respectively, and constitute the second PMOS transistor Q2 together with the second gate electrode 28. The N.sup.+ -type impurity region 26 constitutes the common bias electrode of the first and second PMOS transistors Q1 and Q2. The N.sup.- -type impurity region 26 is a well pick-up region in which a high-concentration impurity is implanted to enhance a conductivity of the N-type well 21. The N.sup.+ -type impurity region 26 and the first P.sup.+ -type impurity region 22 are connected in common to the external supply voltage source. The second and third P.sup.- -type impurity regions 23 and 24 are connected in common to the sense amplifier through the output line 13. The fourth p.sup.+ -type impurity region 25 is connected to the internal supply voltage source. The first and second gate electrodes 27 and 28 are connected to the first and second input lines 11 and 12, respectively.
The above-mentioned conventional restore circuit in FIGS. 1 and 2 is desirable to maintain the restore voltage on the output line 13 constantly at the internal supply voltage level Vint regardless of a variation in an external supply voltage Vext from the external supply voltage source. However, the conventional restore circuit in FIGS. 1 and 2 has a disadvantage in that the second PMOS transistor Q2 is degraded in drive capability due to a voltage increase in the bias electrode with an increase in the external supply voltage Vext. The degradation in the drive capability of the second PMOS transistor Q2 deteriorates a write operation of the sense amplifier for changing a low logic level on the bit line to a high logic level.
Referring to FIG. 3, there is shown a circuit diagram of another example of a conventional restore circuit for a semiconductor memory device. The conventional restore circuit in FIG. 3 has been proposed to overcome the above problem with the conventional restore circuit in FIG. 1.
As shown in FIG. 3, the conventional restore circuit comprises a first PMOS transistor Q3 having its gate for inputting a first control signal from a first input line 31, and a second PMOS transistor Q4 having its gate for inputting a second control signal from a second input line 32. The first PMOS transistor Q3 has its source and bias electrode connected in common to an external supply voltage source and its drain connected to an output line 33, which is connected to a sense amplifier (not shown). When the first control signal from the first input line 31 is low in logic, the first PMOS transistor Q3 is turned on and then remains at its ON state until a restore voltage of a precharge level Vint/2 on the output line 33 is boosted to an internal supply voltage Vint from an internal supply voltage source. As a result, the first PMOS transistor Q3 acts to prevent the restore voltage on the output line 33 from being varied above the internal supply voltage Vint from the internal supply voltage source.
The second PMOS transistor Q4 has its source and bias electrode connected in common to the internal supply voltage source and its drain connected to the output line 33. When the second control signal from the second input line 32 is low in logic, the second PMOS transistor Q4 is turned on to transfer the internal supply voltage Vint from the internal supply voltage source to the output line 33. As a result, the second PMOS transistor Q4 acts to maintain the restore voltage on the output line 33 at the internal supply voltage level Vint. The second PMOS transistor Q4 remains at its ON state for an interval from the turning-on of the first PMOS transistor Q3 to a low to high transition of the second control signal after the turning-off of the first PMOS transistor Q3.
FIG. 4 is a sectional view illustrating a structure of the conventional restore circuit for the semiconductor memory device in FIG. 3. As shown in this drawing, a first N-type well 42 and a P-type well 41 are formed over a semiconductor substrate 40. Formed in the first N-type well 42 are first and second P.sup.+ -type impurity regions 44 and 45 and a first N.sup.+ -type impurity region 46. A first gate electrode 51 is formed over a channel region between the first and second P.sup.+ -type impurity regions 44 and 45. The first and second P.sup.+ -type impurity regions 44 and 45 are source and drain regions, respectively, and constitutes the first PMOS transistor Q3 together with the first gate electrode 51.
A second N-type well 43 and a third P'-type impurity region 47 are formed in the P-type well 41. Formed in the second N-type well 43 are fourth and fifth P.sup.+ -type impurity regions 48 and 49 and a second N.sup.- -type impurity region 50. A second gate electrode 52 is formed over a channel region between the fourth and fifth P'-type impurity regions 48 and 49. The fourth and firth P.sup.+ -type impurity regions 48 and 49 are drain and source regions, respectively, and constitute the second PMOS transistor Q4 together with the second gate electrode 52.
The first and second N.sup.+ -type impurity regions 46 and 50 constitute the bias electrodes of the first and second PMOS transistors Q3 and Q4, respectively. The first N.sup.+ -type impurity region 46 is a well pick-up region in which a high-concentration impurity is implanted to enhance a conductivity of the first N-type well 42. Similarly, the second N.sup.+ -type impurity region 50 is a well pick-up region in which a high-concentration impurity is implanted to enhance a conductivity of the second N-type well 43. The first N'-type impurity region 46 and the first P'-type impurity region 44 are connected in common to the external supply voltage source. The second and fourth P'-type impurity regions 45 and 48 are connected in common to the sense amplifier through the output line 33. The fifth P'-type impurity region 49 and the second N.sup.+ -type impurity region 50 are connected in common to the internal supply voltage source. The first and second gate electrodes 51 and 52 are connected to the first and second input lines 31 and 32, respectively. The third P.sup.- -type impurity region 47 is a well pick-up region for enhance a conductivity of the P-type well 41. The third P.sup.+ -type impurity region 47 is connected to a ground voltage source Vss to prevent a latch-up phenomenon of the second PMOS transistor Q4.
However, the above-mentioned conventional restore circuit in FIG. 3 has a disadvantage in that a latch-up phenomenon occurs when an external supply voltage Vext from the external supply voltage source is instantaneously raised while it is transferred to the output line 33 through the first PMOS transistor Q3. The latch-up phenomenon signifies that the restore voltage on the output line 33 is transferred to the internal supply voltage source. At this time, the restore voltage on the output line 33 exceeds a level of the internal supply voltage Vint+a voltage for turning on a PN junction between the drain and the bias electrode. In order to prevent such a latch-up phenomenon, the P-type well 41 is provided in addition to the construction of FIG. 3, as shown in FIG. 4. However, additional manufacturing processes are required to provide the P-type well 41 for preventing the latch-up phenomenon.